Il messagio alla redazione del sito RSE è stato inviato
Il messaggio al referente RSE è stato inviato
i dati sono stati inseriti correttamente. Per attivare la registrazione, seleziona il link nel testo del messaggio appena inviato all’indirizzo email specificato.
C I R E D Session Number 1 SIMULATIONS AND ELECTRICAL TESTING OF SUPERCONDUCTING FAULT CURRENT LIMITER PROTOTYPES L. Martini, M. Bocchi, R. Dalessandro, M. Levati, V. Rossi CESI Italy email@example.com A growth in the generation of electrical energy and an increased interconnection of the networks lead to higher fault currents. Therefore there is a considerable interest in devices which are capable of limiting fault currents. The superconducting Fault Current Limiter (SFCL) is an innovative device of particular interest to electricity companies since it is aimed to maintain fault current levels on electricity networks to acceptable values, i.e. within electrical component design limits. There are a large number of benefits, which could be attained from the use of this device to both network operators and producers. These benefits include ability to connect generators to plant which would otherwise need to be up-rated, increased network flexibility and reliability due to interconnection of the network, and deferring of reinforcement costs for network operators. The use of high temperature superconductors (HTS) allows the fabrication of effective SFCL devices with different configurations. In this work, we report on simulations and electrical testing of resistive type SFCL prototypes developed in the framework of an Italian R&D Project (LIMSAT). The resistive type design for SFCL has been selected because the basic concept of a resistive SFCL is very simple and benefits from the sudden increase of the resistance from virtually zero to a finite value during the transition phase of the HTS to its non-superconducting state. Moreover, at present there is a general consensus about the potential of its scalability to SFCL devices with high rating. Short circuit testing of several HTS windings has been carried out at CESI facility to ascertain the potential of SFCL. In particular, prospective fault currents, 40 times larger than the nominal current value, have been applied for 40-160ms on LV SFCL prototypes. As a result, prospective peak short circuit current up to 5kA has been effectively reduced to 300A- 800A depending of applied voltage. Time evolution of limited current, voltage across SFCL models, released energy and heating phenomenon is also reported and deeply analysed. Results of simulations are very satisfactory and fully describe the behaviour of SFCL devices made by BSCCO-2223 composite tapes at nominal and limiting conditions. These results are very important to study the behaviour and to evaluate the impact of SFCL devices on MV and HV networks and also to give useful hints to the design of practical SFCL devices. Short circuit test results on a small scale SFCL single-phase prototype showed the excellent current limiting capability of the HTS winding since it provides fault current limiting actions in the first half of cycle (t<5ms), reducing effectively short circuit currents to much smaller current amplitudes. This work is supported by the Research Fund for Italian Electrical System established with Ministry of Industry Decree DM 26/1/2000. PUBBLICATO A5007373 (PAD – 613960)PUBBLICATO A5007373 (PAD – 613960)PUBBLICATO A5007373 (PAD – 613960)PUBBLICATO A5007373 (PAD – 613960)PUBBLICATO A5007373 (PAD – 613960)PUBBLICATO A5007373 (PAD – 613960)
31 Dicembre 2005
Applicazioni di limitatori di corrente SAT (Superconduttori ad Alta Temperatura) (LIMSAT)